1. Field of the Invention
The present invention relates to a delay circuit for delaying and outputting an input signal.
2. Description of the Related Art
Description is given of a conventional delay circuit. FIG. 7 is a diagram illustrating the conventional delay circuit. FIG. 8 is a time chart illustrating delay time periods occurring in the conventional delay circuit.
If an input signal Vin changes from Low to High, because of an inverter 91, respective gate voltages of a P-type metal oxide semiconductor (PMOS) transistor 92 and an N-type metal oxide semiconductor (NMOS) transistor 95 become Low. Accordingly, the PMOS transistor 92 is turned ON while the NMOS transistor 95 is turned OFF. Then, the PMOS transistor 92 charges a capacitor 96 so that an internal voltage Vx may increase gradually. After a delay time period Tx occurring in the case of the input signal Vin changes from Low to High has elapsed since the input signal Vin became High, the internal voltage Vx becomes equal to or higher than an inverting threshold voltage Vti of a buffer 97. Then, an output signal Vout becomes High.
On the other hand, if the input signal Vin changes from High to Low, because of the inverter 91, the respective gate voltages of the PMOS transistor 92 and the NMOS transistor 95 become High. Accordingly, the PMOS transistor 92 is turned OFF while the NMOS transistor 95 is turned ON. Then, the NMOS transistor 95 discharges the capacitor 96 so that the internal voltage Vx may decrease gradually. After a delay time period Ty occurring in the case of the input signal Vin changes from High to Low has elapsed since the input signal Vin became Low, the internal voltage Vx becomes lower than the inverting threshold voltage Vti of the buffer 97. Then, the output signal Vout becomes Low (see, for example, JP 2007-096661 A (FIG. 5)).
In the conventional technology, if a power supply voltage VDD fluctuates, the inverting threshold voltage Vti of the buffer 97 including an inverter (not shown) or the like also fluctuates. As a result, the delay time period Tx occurring in the case of the input signal Vin changes from Low to High and the delay time period Ty occurring in the case of the input signal Vin changes from High to Low fluctuate as well.
Besides, due to manufacturing fluctuations in PMOS transistor (not shown) and NMOS transistor (not shown) included in the buffer 97, there is a risk that the inverting threshold voltage Vti may not be set to a voltage (VDD/2), which results in a problem that the delay time period Tx occurring in the case of the input signal Vin changes from Low to High and the delay time period Ty occurring in the case of the input signal Vin changes from High to Low may differ from each other.